8086 Architecture by Er. Swapnil Kaware
Download as PPTX, PDF5 likes59 views
The document describes the architecture of the 8086 microprocessor. It introduces the 8086, which was released in 1978 and contains 29,000 transistors. It has a 16-bit data bus and 20-bit address bus, and can address up to 1MB of memory. The 8086 architecture contains a Bus Interface Unit (BIU) that handles memory access and instruction fetching, and an Execution Unit (EU) that decodes and executes instructions. It has 14 16-bit registers including general purpose, pointer, segment, and status registers used for arithmetic operations, memory addressing, and instruction execution.
8086 Architecture by Er. Swapnil Kaware
- 1. 8086 ARCHITECTURE Presented By, Er. Swapnil Kaware [email protected] B.E.(Electronics).
- 2. 8086 Overview • Introduced in 1978. • Having Total 40 Pins. • Having Address Bus of 20 bit. • Having Data Bus of 16 bit. • HMOS Microprocessor. • Consumes Low Power (i.e. 360 mA on 5v). • Clock Frequencies of 5,8 &10 MHz. • Contains About 29000 Transistors. • Can Address up to 1 Mbytes of Memory. • It has more than 20,000 instructions. Microprocessor Notes By Er. Swapnil • Provides fourteen 16-Bit registers. Kaware
- 3. 8086 Architecture Microprocessor Notes By Er. Swapnil Kaware
- 4. 8086 Internal Architecture • 8086 internal Architecture contains mainly following two units. • (1). BIU (Bus Interface Unit). • (2). EU (Execution Unit). • BIU contains Instruction queue, Segment registers,Instruction pointer,etc. • EU contains Control circuitry, Instruction decoder, ALU,Pointer and Index register, Flag register,etc. Microprocessor Notes By Er. Swapnil Kaware
- 5. Bus Interface Unit (BIU) • Following functions are supported by BIU. (1). It provides a full 16 bit bidirectional data bus and 20 bit address bus. (2). It sends address of memory or I/O. (3). It fetches instruction from memory. (4). It reads data from port/memory. (5). It writes data into port/memory. (6). It supports instruction queuing . (7). It makes 8086’s interface to the outside world. (8). The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. (9). If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. (10). The BIU also contains a dedicated adder which is used to generate the 20bit physical address. Microprocessor Notes By Er. Swapnil Kaware
- 6. Execution Unit (EU) • Following functions are supported by BIU. (1). The Execution unit is responsible for decoding and executing all instructions. (2). The EU extracts instructions from the top of the queue in the BIU. (3). During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. (4). If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. (5). The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. (6). It tells BIU from where to fetch instructions or data,decodes instructions & execute instructions. By Er. Swapnil Microprocessor Notes Kaware
- 7. 8086’s Fourteen 16-Bit Registers ES Extra Segment BIU registers (20 bit adder) CS Code Segment SS Stack Segment DS Data Segment IP Instruction Pointer AX AH AL Accumulator BX BH BL Base Register CX CH CL Count Register DX DH DL Data Register SP Stack Pointer BP Base Pointer EU registers SI Source Index Register 16 bit arithmetic DI Destination Index Register FLAGS Microprocessor Notes By Er. Swapnil Kaware
- 8. Instruction Queue • It is of 6 Bytes. • To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from memory. • It operates on the principle first in first out (FIFO). • Then all bytes are given to EU one by one. • This pre-fetching operation of BIU may be in parallel with execution operation of EU. • It improves the execution speed of the instruction. Microprocessor Notes By Er. Swapnil Kaware
- 9. Registers of 8086 • Intel 8086 contains following registers: • General Purpose Registers • Pointer and Index Registers • Segment Registers • Instruction Pointer • Status Flags Microprocessor Notes By Er. Swapnil Kaware
- 10. General Purpose Registers • There are four 16-bit general purpose registers: • AX • BX • CX • DX Microprocessor Notes By Er. Swapnil Kaware
- 11. General Purpose Registers • Each of these 16-bit registers are further subdivided into two 8-bit registers. AX AH AL BX BH BL CX CH CL DX DH DL Microprocessor Notes By Er. Swapnil Kaware
- 12. General Purpose Registers • AX Register: AX register is also known as accumulator register that stores operands for arithmetic operation like divided, rotate. • BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment. • CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop counter. • DX Register: DX register is used to contain I/O port address for I/O instruction. Microprocessor Notes By Er. Swapnil Kaware
- 13. Pointer & Index Register • Following four registers are under this category: • (1). Stack Pointer (SP), • (2). Base Pointer (BP), • (3). Source Index (SI), • (4). Destination Index (DI). Microprocessor Notes By Er. Swapnil Kaware
- 14. Pointer & Index Register • Following Registers can also be used as a general Purpose Registers. (1). Stack Pointer (SP) is a 16-bit register pointing to program Stack, also contains 16-Bit offset address. (2). Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based indexed or register indirect addressing. (3). Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation Instructions (4). Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. Microprocessor Notes By Er. Swapnil Kaware
- 15. Segment Register • There are four segment registers in Intel 8086: (1). Code Segment Register (CS), (2). Data Segment Register (DS), (3). Stack Segment Register (SS), (4). Extra Segment Register (ES). Microprocessor Notes By Er. Swapnil Kaware
- 16. Segment Register • A segment register points to the starting address of a memory segment. • For e.g.: • The code segment register points to the starting address of the code segment. • The data segment register points to the starting address of the data segment, and so on. • The maximum capacity of a segment may be up to 64 KB. Microprocessor Notes By Er. Swapnil Kaware
- 17. Segment Register • Code segment (CS):- • It is a 16-bit register containing address of 64 KB segment with processor instructions. • The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. • CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions Microprocessor Notes By Er. Swapnil Kaware
- 18. Segment Register • Stack segment (SS):- • it is a 16-bit register containing address of 64KB segment with program stack. • By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. • SS register can be changed directly using POP instruction. Microprocessor Notes By Er. Swapnil Kaware
- 19. Segment Register • Data segment (DS):- • It is a 16-bit register containing address of 64KB segment with program data. • By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. • DS register can be changed directly using POP and LDS instructions. Microprocessor Notes By Er. Swapnil Kaware
- 20. Segment Register • Extra segment (ES):- • It is a 16-bit register containing address of 64KB segment, usually with program data. • By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. • ES register can be changed directly using POP and LES instructions. • It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS,DS or ES prefix. Microprocessor Notes By Er. Swapnil Kaware
- 21. Concept of Segmented Memory • It allows the memory addressing capacity to be 1 Mbytes. • It allows instruction code,data,stack and portion of program to be more than 64KB long. • It facilitates use of separate memory areas for program, data and stack. • It permits a program or its data to be put in different areas of memory • In this program can be relocated which is very useful in multiprogramming i.e.multitasking becomes easy. Microprocessor Notes By Er. Swapnil Kaware
- 22. Concept of Segmented Memory FFFFFH Highest Address 7FFFFH Top Of Extra Segment 64KB Extra Segment Base ES=7000H 5FFFFH Top Of Stack Segment 64KB 50000H Stack Segment Base SS=5000H 4489FH Top Of Code Segment 64KB 348A0H Code Segment Base CS=348AH 2FFFFH Top Of Data Segment 64KB 20000H Bottom Of Data Microprocessor Notes By Er. Swapnil Segment Kaware
- 23. Instruction Pointer • The Instruction Pointer (IP) in 8086 acts as a Program Counter. • It points to the address of the next instruction to be executed. • Its content is automatically incremented when the execution of a program proceeds further. • The contents of the IP and Code Segment Register are used to compute the memory address of the instruction code to be fetched. • This is done during the Fetch Cycle. Microprocessor Notes By Er. Swapnil Kaware
- 24. Status Flags • Status Flags determines the current state of the accumulator. • They are modified automatically by CPU after mathematical operations. • This allows to determine the type of the result. • 8086 has 16-bit status register. • It is also called Flag Register or Program Status Word (PSW). • There are nine status flags and seven bit positions remain unused. Microprocessor Notes By Er. Swapnil Kaware
- 25. Flag Register (PSW) 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OF DF IF TF SF ZF AF PF CF Carry Flag Undefined Parity Flag Auxiliary Carry Flag Zero Flag Sign Flag Trap Flag Interrupt Flag Direction Flag Overflow Flag Microprocessor Notes By Er. Swapnil Kaware
- 26. Flag Register (PSW) • 8086 has 9 flags and they are divided into two categories: • (1). Condition Flags, • (2). Control Flags. Microprocessor Notes By Er. Swapnil Kaware
- 27. Flag Register (PSW) • Following are the nine flags: Condition Flags Control Flags 1. Carry Flag 1. Trap Flag 2. Auxiliary Carry Flag 2. Interrupt Flag 3. Zero Flag 3. Directional Flag 4. Sign Flag 5. Parity Flag 6. Overflow Flag Microprocessor Notes By Er. Swapnil Kaware
- 28. Flag Register (PSW) • Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF indicates that the result has exceeded the capacity of machine. • Trap Flag (TP): It is used for single step control. • It allows user to execute one instruction of a program at a time for debugging. • When trap flag is set, program can be run in single step mode. • Interrupt Flag (IF): It is an interrupt enable / disable flag. • If it is set, the INTR interrupt of 8086 is enabled and if it is reset then INTR is disabled. • It can be set by executing instruction STI and can be cleared by executing CLI instruction. • Direction Flag (DF): It is used in string operation. • If it is set, string bytes are accessed from higher memory address to lower memory address. • When it is reset, the string bytes are accessed from lower memory address to higher memory address. • It is set with STD instruction and cleared with CLDinstruction. Microprocessor Notes By Er. Swapnil Kaware
- 29. Pin Diagram of 8086 8086 Pin Diagram Microprocessor Notes By Er. Swapnil Kaware
- 30. Function Of Pins of 8086 • AD15-AD0: These are the time multiplexed memory I/O address and data lines. The lines AD0-AD7 carries low order byte of data & AD8-AD15 carries high order byte of data. • A19/S6,A18/S5,A17/S4,A16/S3: These are the time multiplexed address and status lines. • During T1 these are the most significant address lines for memory operations. • During I/O operations, these lines are low. • The S4 and S3 combination indicates which segment register is presently being used for memory accesses. Microprocessor Notes By Er. Swapnil Kaware
- 31. Function Of Pins of 8086 S4 Pin S3 Pin Indication 0 0 Extra Segment 0 1 Stack Segment 1 0 Code or None 1 1 Data Segment BHE (Bus High Enable) /S7: The bus high enable is used to indicate the transfer of data over the higher order ( D15-D8 ) data bus as shown in table. BHE Pin A0 Pin Indication 0 0 Whole Word 0 1 Upper Byte from/to odd address 1 0 Lower Byte from/to even address 1 1 None Microprocessor Notes By Er. Swapnil Kaware
- 32. Function Of Pins of 8086 (1). RD: This signal on low indicates the peripheral that the processor is performing memory or I/O read operation. (2). READY: This is the acknowledgement from the slave device or memory that they have completed the data transfer. (3). INTR-Interrupt Request: This is a triggered input. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. • This can be internally masked by resulting the interrupt enable (IE) flag. • This signal is active high and internally synchronized. Microprocessor Notes By Er. Swapnil Kaware
- 33. Function Of Pins of 8086 (4). TEST: This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. (5). CLK- Clock Input: The clock input provides the basic timing pulses for processor operation and bus control activity. (6). MN/MX: The logic level at this pin decides whether the processor is to operate in either minimum mode or maximum mode. Microprocessor Notes By Er. Swapnil Kaware
- 34. Operating Modes Of 8086 • 8086 microprocessors can be configured to work in either of the two modes: • (1). Minimum Mode, • (2). Maximum Mode. • Minimum mode: – Pull MN/MX to logic 1. – Typically smaller systems and contains a single microprocessor. • Maximum mode: – Pull MN/MX logic 0. – Larger systems with more than one microprocessor. Microprocessor Notes By Er. Swapnil Kaware
- 35. Common Signals In Both Mode Microprocessor Notes By Er. Swapnil Kaware
- 36. Signals In Minimum Mode (1). Address Latch Enable (ALE): is a pulse to logic 1 that gives signal to external circuitry there is a valid address available on the bus (AD0-AD15). (2). IO/M line: When low indicates I/O device is accessed & When high indicates memory device is accessed. (3). DT/R line: indicates direction of data to be select. i.e. when goes low indicates that the processor receives the data & when goes high indicates that the processor sends the data. (4). BHE (Bank High Enable) line : when goes low indicates that there is transfer of data on lower order bus (D0-D7) & when goes high indicates that there is transfer of data on higher order bus (D8-D15). Microprocessor Notes By Er. Swapnil Kaware
- 37. Signals In Minimum Mode (5). RD line: when goes low indicates the processor to read data from memory or I/O devices. (6). WR line: when goes low indicates the processor to write data to memory or I/O devices. (7). DEN line: when goes low indicates that there is availability of valid data on AD0-AD15. (8). Ready line: when goes high indicates that the peripheral device is ready to transfer data. Microprocessor Notes By Er. Swapnil Kaware
- 38. Signals In Minimum Mode (9). INTR: (Interrupt request): it is used to determine the availability of request. (10). INTA: when goes low processor acknowledges the interrupt. (11). TEST: Processor suspends operation when goes high & resumes the operation when goes low. It is used to synchronize the processor to external events. (12). NMI: (Non Maskable interrupt): it can not be delayed or rejected i.e. can not be recognized. (13). RESET: when goes low processor terminates the current activity & goes to reset state. Microprocessor Notes By Er. Swapnil Kaware
- 39. Signals In Maximum Mode (14). LOCK: when goes low (i.e. active) then it prevents other processors from being using the system bus. (15). QS0 and QS1 (queue status signals) : informs about the status of the queue i.e. whether the queue is empty or not. QS1 QS0 Indication 0 0 No operation 0 1 First byte of the opcode from the queue 1 0 Empty queue 1 1 Subsequent byte from the queue (16). RQ/GT0 and RQ/GT1: These pins are used to force the processor to release the local bus at the end of processors current bus cycle. Microprocessor Notes By Er. Swapnil Kaware
- 40. Signals In Maximum Mode (17). S2, S1, S0 – Status Lines: These are the status lines which reflect the type of operation, being carried out by the processor. S0 S1 S2 Indication 0 0 0 Interrupt Acknowledge 0 0 1 Read I/O port 0 1 0 Write I/O port 0 1 1 Halt 1 0 0 Code Access 1 0 1 Read memory 1 1 0 Write memory 1 1 1 Passive Microprocessor Notes By Er. Swapnil Kaware
- 41. Concept of Pipelining • In this technique we can execute more than one instruction at the same time. • In this fetching, decoding & execution operations are performed parallel with each other. • In 8086 microprocessor pipelining concept is introduced with the help of 6-Byte instruction queue. • Number of clock cycles required is less. • Execution process of instructions becomes fast as compared to other processors. • It increases the efficiency of 8086 microprocessor. Microprocessor Notes By Er. Swapnil Kaware
- 42. Concept of Pipelining Microprocessor Notes By Er. Swapnil Kaware
- 43. Features of 8284 Clock Generator (1). High performance CMOS Clock Generator. (2). Total number pins are 18. (3). Designed to service the requirements of both CMOS and NMOS microprocessors. (4). Operating frequency is up to 25MHz. (5). Works on 5V Power Supply. (6). Very Low Power Consumption. (7). Works on three logic levels. (a). Clock, (b). Ready ,(c). Reset. Microprocessor Notes By Er. Swapnil Kaware
- 44. 8284 Clock Generator Microprocessor Notes By Er. Swapnil Kaware
- 45. 8284 Clock Generator Microprocessor Notes By Er. Swapnil Kaware
- 46. Working of 8284 Clock Generator • There are three main important functions of 8284 clock generator. • (1). It generates system clock for 8086 microprocessor. • (2).it provides ‘READY’ signal for 8086 microprocessor. • (3).it provides ‘RESET’ signal for 8086 microprocessor. Microprocessor Notes By Er. Swapnil Kaware
- 47. Interfacing of 8284 clock generator with 8086 microprocessor Microprocessor Notes By Er. Swapnil Kaware
- 48. Clock Logic Description of 8284 Clock Generator • This logic generates following three signals. • (1).CLK, (2).OSC, (3).PCLK. • EFI (External Frequency Input): It supplies the timing pulses whenever the F/C (Frequency/Crystal) pin is high. • CLK: The clock output pin provides CLK input signal to the 8086 microprocessors. • This pin has an output signal that is one-third of the crystal. • It has a 33% duty cycle, which is required by the 8086 microprocessors. Microprocessor Notes By Er. Swapnil Kaware
- 49. Clock Logic Description of 8284 Clock Generator • PCLK (Peripheral Clock): This signal is one-sixth of the crystal. • It has a 60% duty cycle. • The PCLK output provides a clock signal to the peripheral devices in the system. • OSC: The frequency of the oscillator is equal to the crystal frequency. • CSYNK (Clock Synchronization): When this signal is active then all internal counters becomes reset & When this signal is deactivate then all internal counters are allowed to resume counting the clock pulses. Microprocessor Notes By Er. Swapnil Kaware
- 50. Ready Logic Description of 8284 Clock Generator • AEN1 & AEN2 (Address Enable): This pins are provided to qualify/validate the ready signals. i.e. RDY1 & RDY2. • RDY1 and RDY2 (Ready): Wait states required for 8086 microprocessor are generated by this pins. • RDY1 input is works in conjunction with the AEN1. • RDY2 input is works in conjunction with the AEN2. Microprocessor Notes By Er. Swapnil Kaware
- 51. Reset Logic Description of 8284 Clock Generator • RES: The reset input is an active-low input to the 8284 clock generator. • This pin is often connected an RC network that provides power-on resetting. • RESET: This output pin is connected to the 8086 microprocessors RESET input. Microprocessor Notes By Er. Swapnil Kaware
- 52. 8288 Bus Controller Microprocessor Notes By Er. Swapnil Kaware
- 53. 8288 Bus Controller • 8288 bus controller is required to generate necessary control signals when 8086 microprocessor is interfaced with memory or I/O devices in maximum mode. • It generates control signals required for reading & writing input or output. • It generates control signals i.e.(DT/R & DEN) required for communicating with transceiver. Microprocessor Notes By Er. Swapnil Kaware
- 54. Maximum mode interface with 8288 bus controller. Microprocessor Notes By Er. Swapnil Kaware
- 55. Timing Diagram Concepts (1). Clock Cycle: It is the speed at which how much things it can process in a certain amount of time. (2). Machine Cycle: It is defined as the time required to complete the one operation. (3). Instruction Cycle: It is defined as the time required to complete the execution of an instruction. (4). T-state: It is defined as subdivision of operation performed in one clock period. Microprocessor Notes By Er. Swapnil Kaware
- 56. Timing Diagram of 8086 ‘Read’ cycle in minimum mode Microprocessor Notes By Er. Swapnil Kaware
- 57. Timing Diagram of 8086 ‘Write’ cycle in minimum mode Microprocessor Notes By Er. Swapnil Kaware
- 58. Timing Diagram of 8086 ‘Read’ cycle in maximum mode Microprocessor Notes By Er. Swapnil Kaware
- 59. Timing Diagram of 8086 ‘Write’ cycle in maximum mode Microprocessor Notes By Er. Swapnil Kaware
- 60. END OF 8086 ARCHITECTURE SESSION Microprocessor Notes By Er. Swapnil Kaware